Embodiments of the present invention relate to a semiconductor device including a buried gate, and more particularly to a semiconductor device increasing a contact area between a bit line contact and an active region to improve external resistance of the bit line contact.
Semiconductor devices are designed to be used for particular purposes by implanting impurities, and/or depositing a new material at a predetermined region of a silicon wafer. A semiconductor memory device may include a large number of elements to carry out given purposes, for example, transistors, capacitors, resistors, and the like. Individual elements are interconnected through a conductive layer so that data or signals are communicated therebetween.
With the increasing development in technologies for manufacturing semiconductor devices, research has been conducted into a method for forming more chips on one wafer by increasing the integration degree of semiconductor devices. To increase the integration degree of such semiconductor devices, a minimum feature size required for the design rules of semiconductor devices becomes smaller.
An active region of the semiconductor device having a 6F2-sized unit cell (where, F is a minimum feature size) may be configured in an elliptical shape, with a long axis of the active region tilted by a predetermined angle with respect to the progressing direction of bit lines in such a manner that the active region includes a buried gate structure in which a word line is buried in a semiconductor substrate.
In the 6F2-sized semiconductor device, a bit line contact may be coupled to an active region between buried gates, and bit lines may be formed to be connected to the top part of the bit line contact.
However, as the unit cell is reduced in size due to higher integration of the semiconductor device, the bit line contact is also reduced in size, possibly resulting in the occurrence of high resistivity. As a result, may be difficult to normally write and read data in and from a cell.
Therefore, there is needed a method for solving the high-resistivity problem caused by reduction in the bit line contact size.